Top 10 Low Power VLSI Projects

The term "Very Large-Scale Integration Technology" (VLSI) refers to the process of creating integrated circuits (ICs) by logically fusing thousands of transistors onto a single chip using various logic circuits. When compared to circuits using traditional ICs, these ICs ultimately lower the amount of circuit area that is occupied. The primary issues of the VLSI design are computational power and space utilisation. 

For both students and academics, putting VLSI concepts into practise offers up a demanding and promising profession. FPGA applications, ASIC architectures, and SOCs are a few of the newest and most popular VLSI trends. Students that are really looking for projects in this discipline may find a list of some VLSI projects below.

The top 10 low power VLSI projects to learn from and put their talents to the test are as follows:

1. Low Power High Speed 4 Dimension FinFET SRAM

Elements of memory are found in the majority of chips. We thus convert from MOSFETs to FinFETs to reduce the size of memory chips, boost speed, minimise (Drain-induced barrier lowering) DIBL and short channel effects at lower technological nodes.

As FinFETs have a lower threshold voltage, we have total channel control. High drain current, quicker switching times, and low power consumption are just a few of the additional benefits of employing FinFETs over MOSFETs. 

This article compares the speeds of 6T MOSFET and 6T FinFET SRAM cells. Using H-45nm Spice's technology, all designs are executed.

2. Design of Two Stage Operational Amplifier and Implementation of Flash ADC

Flash Analog to Digital Converter with 3-bit Resolution is implemented in this article. Flash ADC's main issue is that as the number of resolution bits rises, the area of the circuit as well as its power consumption rise.

The use of portable, long-lasting battery digital systems is advocated. Creating apps with lower power requirements is the only way to do this. By improving the encoder circuitry, we primarily focused on reducing the ADC's power consumption in this research.

Using Tanner EDA Cadence Virtuoso tools and 180nm technology, the whole design is put into practise. Calculations and comparisons are made for Flash ADC performance metrics including latency and average power.

3. Design and Implementation of 4-bit and 8-bit KSA in 18nm FinFET Technology

This work is implemented in the technology node of the 18nm FinFET model. It works quicker than its rivals, which results in a high PDP (Power-Delay Product). The adder's operations are assessed using simulations of random input data, and it is created and designed for bit lengths of 4 and 8.

The adder's building blocks are all examined, and the findings are displayed visually. The collected data is tabulated in order to adequately assess the parameters. Virtuoso cadence is used to execute each design.

4. High-Speed and Area-Efficient Scalable N-bit Digital Comparator

In this research, a high-speed, low-power N-bit digital comparator with efficient use of area is presented. There are two distinct modules in the suggested comparator structure. The Comparative Evaluation Module (CEM) is the first module, and the Final Module (FM) is the second.

The regular structure of repeating logic cells utilised for constructing parallel prefix tree structure is a component of CEM, regardless of the input bit widths. On the basis of the CEM's findings, the FM certifies the final comparison. Tanner EDA is used to implement the design in 180nm technology.

5. Miller Compensation using CMOS OPAMP employing Current Buffer

A mill operator capacitor operational amplifier is built in this research. It is described how the normal door current cushion is connected to the design approach of the two-stage CMOS functional intensifiers using Mill operator capacitor. The use of this circuit eliminates recurrence since the lower frequencies are higher than the channel.

By comparing the miller compensation to the uncompensated method, the compensation technique was presented, and the optimal gain features were subsequently enhanced. Using GPDK 45nm technology, this circuit is built on the Cadence Virtuoso platform.

6. A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS

Low-power, high-speed operation can be accomplished with a Sensing Amplifier based Flip Flop (SAFF). The power and latency of the flip-flop are significantly decreased by using a new sense-amplifier stage as well as a new single-ended latch stage. By implementing MTCMOS optimisation, the suggested SAFF may offer low voltage operation.

The proposed SAFF's power and latency are lower than those of the current Master Slave Flip Flop (MSFF). In comparison to the standard SAFF and MSFF, the suggested SAFF's power-delay product improves, and the proposed flip-area flop's decreases.

Even with low power supply voltages, the suggested SAFF could still operate reliably. Nevertheless, we are employing 45nm technology in this design, which enables us to provide 1 LVT and yet get the desired output.

7. Novel Design Methodologies for CNFET-Based Ternary Sequential Logic Circuits

A brand-new design approach for a ternary D-flipflop is put forth in this research work. It involves the usage of two STIs and a ternary buffer, which are powered by two separate power sources. STIs, successor-predecessor circuits, and ternary buffers are used to build two hybrid architectures for ternary D flipflop devices that have also been presented. 

Using these ternary D-flipflop designs, ternary 3- trit synchronous and asynchronous counters are designed in this paper. All the designs are implemented in H-spice using 45 nm technology.

8. Algorithm Level Error Detection in Low Voltage Systolic Array

This summary describes a method that, when used at the transistor level, can result in energy savings through decreased voltage operation. We are going to create a systolic array matrix multiplier in this specific implementation so that ABFT may be integrated and used to find flaws. 

When implemented at a low level, this specific method utilises Algorithm Based Fault Tolerance (ABFT) to integrate timing problems into a digital architecture. The method has been investigated using a systolic array matrix multiplier working at lower voltages, detecting faults immediately to prevent energy-demanding memory round-trips. 

Verilog HDL was used for the solution's design and development, and the Xilinx Vivado2018.3/Xilinx ISE14.7suite was taken into consideration to extract the simulation results of the implemented design.

9. Low Power, High Performance PMOS Biased Sense Amplifier

An amplifier with a PMOS bias is suggested in this study. As far as the performance, usability, and dependability of the memory circuits are concerned, sense amplifiers play a key role. With a very high output impedance, the suggested circuit is a PMOS biased sensing amplifier. 

Moreover, it accomplishes the same functions as traditional circuits but with less power dissipation and sensory latency. Tanner EDA/Cadence Virtuoso was used to simulate and evaluate the recommended sense amplifiers' overall performance while using the 180 nm library settings.

10. Low Power 3-Bit Encoder Design using Memristor

In three alternative configurations such as CMOS logic, memristor logic, and pseudo NMOS logic, the design of an encoder is presented. Three bits make up the encoder that was created.

Comparing memristor logic with cmos and pseudo-nmos logic, the suggested 3-bit encoder dissipates less power. Using LTspice, the full encoder schematic in these three combinations is simulated.