Novel Design Methodologies for CNFET-Based Ternary Sequential Logic Circuits

Project Code :TVPGBE147


The main objective of this paper is to reduce the power consumption in the implementation of Ternary Sequential Circuits with the use of CNTFET Methodology.


The quest for efficient technologies beyond the traditional CMOS(Complementary-Metal-Oxide-Semiconductor) technology has led researchers to explore newer technologies like the CNFET(Carbon-Nanotube-Field-Effect-Transistor). CNFETs are being used to design and implement various ternary logic circuits. Multi value d logic(MVL)requires multiple threshold voltages that are possible to obtain using CNFETs by modifying the physical dimensions of their CNTs (Carbon Nano Tubes). The ternary sequential logic circuits like ternary D-latch, D-flipflop, and counters existing in literature have been implemented either using STIs (Standard Ternary Inverters) or successor-predecessor circuits. This paper proposes a new design methodology for a ternary D-flipflop that uses a ternary buffer and two STIs designed using two power supplies. Two hybrid architectures for ternary D flipflop designs have also been proposed that are implemented using a combination of ternary buffer, STIs and successor-predecessor circuits. Using these ternary D-flipflop designs, ternary 3- trit synchronous and asynchronous counters are designed in this paper. All the designs are implemented  in H-spice using 45 nm technology .

Index Terms—CNFET, D-flipflop, D-latch, STI, ternary logic .

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram


Software Requirements:
·        H-spice
·        Technology files: 45nm
Hardware Requirements:
·        Microsoft® Windows XP
·        Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
·        512 MB RAM
·        100 MB of available disk space

Learning Outcomes

  • Introduction to D flip flop
  • Knowledge on flip flop

·         MOS Fundamentals

·         NMOS/PMOS/CMOS Technologies

·         How to design circuits using Transistor logic?

·         Transistor level design for latch

·         Introduction to Analog Electronics

·         Importance of synchronous counter

·         Applications in real time

  • H-spice tool for design and simulation
  • Solution providing for real time problems

·         Project Development Skills:

o   Problem Analysis Skills

o   Problem Solving Skills

o   Logical Skills

o   Designing Skills

o   Testing Skills

o   Debugging Skills

o   Presentation skills

o   Thesis Writing Skills

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