Algorithm Level Error Detection in Low Voltage Systolic Array

In this brief an approach is proposed to achieve energy savings from reduced voltage operation when implemented in transistor level. In this particular implementation we are going to design a systolic array matrix multiplier where ABFT can be integrated such that it can detect faults. This particular solution detects timing-errors by integrating Algorithm Based Fault Tolerance (ABFT) into a digital architecture when implemented at low level. The approach has been studied with a systolic array matrix multiplier operating at reduced voltages, detecting errors on-the-fly to avoid energy demanding memory round-trips. The design and development of the solution has been done using Verilog HDL and to extract the simulation results of implemented design Xilinx Vivado2018.3/Xilinx ISE14.7suite was considered.