Also Available Domains Transistor Logic|Cadence EDA|Tanner EDA
The aim of this paper is to implement a Flash ADC structure consists of a resistive ladder network, comparators, and the thermometer to a binary encoder. Encoder structure in this paper is implemented using 2:1 mux based on switch logic.
In this paper, Flash Analog to digital converter is implemented whose resolution is 3-bits.The major problem that usually appears in flash ADC is as the number of resolution bits increases, the Area, as well as the power consumption of the circuit, also increases. It is preferred to have digital systems that are portable and have prolonged battery life. This can be only possible by developing applications that consume less power. In this paper, we principally concentrated to lessen the power consumption of the ADC by optimizing encoder circuitry. The entire design is implemented using Tanner EDA\Cadence Virtuoso tools employing 180nm technology. Performance parameters of Flash ADC such as delay as well as average power are calculated and compared.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Software Requirements:
Hardware Requirements: