VLSI Design of Majority Logic based Wallace Tree Multiplier

This paper presents a novel approach to the Very Large Scale Integration (VLSI) design of a Wallace Tree Multiplier, leveraging majority logic as a fundamental building block. Multipliers are critical components in various digital signal processing and arithmetic units, and their efficient design is pivotal for achieving high-performance computing systems. The proposed Wallace Tree Multiplier design harnesses the power of majority logic to enhance both speed and area efficiency, making it particularly suitable for modern computing applications.

The key innovation in our approach lies in the replacement of traditional binary adders with majority logic-based adder cells within the Wallace Tree structure. Majority logic exploits the inherent redundancy in binary addition, allowing for a reduction in the number of full adder cells and, consequently, a substantial decrease in area overhead. We also introduce an optimized carry propagation scheme to further improve the critical path delay.

Keywords— Majority Gates, Wallace Tree Multiplier, V-HDL.