Verilog Code Generation of Hierarchical Design Using LLMs

Project Code :TVMAFE722

Objective

1. To explore the capability of Large Language Models (LLMs) in generating accurate and synthesizable Verilog HDL for hierarchical digital designs. 2. To evaluate the efficiency and reliability of LLM-generated Verilog code compared to manually written RTL in terms of correctness, modularity, and hardware resource utilization.

Abstract

With the increasing complexity of VLSI systems, hierarchical hardware design has become essential to manage large-scale digital circuits efficiently. Verilog HDL is widely used for describing such hierarchical designs; however, manual code development is time-consuming and error-prone. Recent advancements in Large Language Models (LLMs) have enabled automated code generation by understanding high-level design specifications. This project focuses on the automatic generation of hierarchical Verilog code using LLMs. The proposed approach translates natural language or structured design descriptions into syntactically correct and modular Verilog code. By leveraging LLM capabilities, the system improves productivity, reduces human errors, and accelerates the hardware design cycle, making it suitable for modern FPGA and ASIC-based design flows.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Microsoft® Windows 10 / Windows 11 (64-bit)
Intel® Core™ i5 / i7 Processor or equivalent
Minimum 8 GB RAM
Minimum 500 MB free disk space

Learning Outcomes

- Understand hierarchical hardware design concepts
- Learn automated Verilog code generation techniques
- Gain exposure to Large Language Models in VLSI design
- Analyze benefits of AI-assisted design automation
- Develop practical knowledge of Verilog HDL