Truncated Booth Multiplier Design Of Approximate Compressors Using Verilog Hdl

Project Code :TVMAFE574

Objective

The main objective of this project is to implement 16-bit booth multiplier using radix-256 in order to improvise performance.

Block Diagram

Learning Outcomes

LEARNING OUTCOMES:

  • Basics of Digital Electronics.
  • Introduction to Verilog Coding.
  • Different modeling styles in Verilog.

o   Data Flow modeling.

o   Structural modeling.

o   Behavioral modeling.

o   Mixed level modeling.

Β·       About approximation computing.

  • Applications in real time.

Β·         Xilinx Vivado 2018.3/Xilinx ISE 14.7 Suite for design and simulation.

Β·         Generation of Netlist.

Β·         Solution providing for real time problems.

Β·         Project Development Skills:

o   Problem Analysis Skills.

o   Problem Solving Skills.

o   Logical Skills.

o   Designing Skills.

o   Testing Skills.

o   Debugging Skills.

o   Presentation Skills.

o   Thesis Writing Skills.

Demo Video

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