The proposed study aims to provide a 64-bit approximation multiplier with high throughput and low latency for cutting-edge DSP applications.
It is possible to use a variety of computer arithmetic systems to carry out a complex multiplier. The efficiency of an FPGA-VLSI processor relies on how quickly its digital signal processing operations can be carried out. In order to achieve both high accuracy and speed, the authors of this work offer a concept for a 64-bit approximation multiplier technique that utilizes compressors and partial product multipliers. For artificial intelligence (AI) based FPGA-VLSI applications, approximate multipliers are among the fastest multipliers available. The suggested study reveals a 64-bit approximation to a 64-bit multiplicator. To implementation of the proposed 64-bit digital approximate multiplier, we are using the partial product or dadbased multiplication technique; in which the 64 bit multiplication process complete in the partial form. 64 bit split into the 32, 16, 8, 4 and 2 bit multiplication. The FPGA integrated circuit utilized for the simulation is a member of the virtex 7 family.
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Software Requirements:
· Xilinx ISE Vivado
· HDL: Verilog
Minimum Hardware Requirements:
· Microsoft® Windows 7
· Intel® i3 or equivalent
· 4 GB RAM
· 100 MB of available disk space
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