Performance Analysis of MAC Unit with Various Parallel Adders

Project Code :TVMAFE714

Objective

Evaluate Different Parallel Adders in MAC Context • Analyze how various parallel adder architectures (e.g., Carry Look-Ahead, Carry Select, Carry Save, Carry Skip, Parallel-Prefix adders) affect the performance of a MAC unit. • Determine which adder type offers the best trade-off of delay, power, and area when used in the accumulation (adder) stage of a MAC.

Abstract

The Multiply-Accumulate (MAC) Unit is a crucial component in all DSP Applications, due to its ability to perform high speed arithmetic operations. This research aims to design and implement an 8-bit MAC Unit capable of performing multiplication and accumulation operations. The MAC Unit employs the same multiplier but integrates different adders such as Kogge-Stone, Ladner-Fischer, Carry Look-Ahead adder, and Ripple Carry Adder. The structures were formed using Verilog Hardware Description Language (HDL) and implemented on Xilinx Vivado

Keywords—MAC Unit, Kogge-Stone, Ladner-Fischer, Verilog HDL, Multiplier

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Specifications

Software Requirements

Xilinx Vivado Design Suite (2020.2 or later)
Verilog HDL for RTL design and implementation
Vivado Simulator (XSIM) for functional and timing verification

Hardware Requirements

Microsoft® Windows 10 / Windows 11 (64-bit)
Intel® Core™ i5 / i7 Processor or equivalent
Minimum 8 GB RAM
Minimum 500 MB free disk space

Learning Outcomes

Understand the architecture and operation of a Multiply–Accumulate (MAC) unit and its role in DSP and signal processing applications.
Gain knowledge of different parallel adder architectures (Ripple Carry, Carry Look-Ahead, Carry Save, Brent–Kung, Kogge–Stone, etc.) and their integration within a MAC unit.
Design and implement MAC units with multiple adder variants using Verilog HDL.
Analyze and compare performance metrics such as area, delay, power consumption, and throughput for each parallel adder–based MAC design.
Learn to use Xilinx Vivado for synthesis, simulation, and timing/power analysis of FPGA-based MAC architectures.
Develop the ability to evaluate trade-offs between speed, hardware complexity, and power efficiency in high-performance arithmetic units.