Modified FIR Filter and High Speed Adder for Signal Processing Applications

Project Code :TVMAFE696

Objective

The objective of this project is to design and implement a modified FIR filter integrated with a high-speed adder for efficient signal processing applications. It focuses on enhancing the filter’s performance by reducing computational delay and improving processing speed through optimized adder architecture. The design will be simulated and verified to evaluate key parameters such as area, power consumption, and accuracy. Comparative analysis will be carried out to demonstrate improvements over conventional FIR filter and adder implementations. The overall goal is to develop a high-performance, low-latency, and energy-efficient FIR filter suitable for real-time digital signal processing systems.

Abstract

Abstract:

Low-power, high-performance digital signal processing is becoming more and more crucial. The most commonly used basic components of DSP systems are filters with finite impulse response. These complete filter topologies were created utilizing the Modified Carry Select Adder and Ripple Carry Adder in accordance with the parallel FIR digital filter's performance analysis. Since adders are less costly than multipliers in terms of silicon area, the switch is feasible. We will compare the performance of parallel FIR filter topologies based on Carry Select Adder and Ripple Carry Adder.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.