Implementation of an Enhanced RC6 Algorithm for Securing Data Using Verilog

With the rapid advancement of digital communication and data storage, ensuring robust security mechanisms has become crucial. The RC6 encryption algorithm, an extension of the RC5 cipher, offers enhanced security and efficiency, making it suitable for high-speed cryptographic applications. This paper presents the implementation of an enhanced RC6 algorithm using Verilog, focusing on optimizing hardware efficiency, reducing latency, and increasing throughput. The proposed design leverages hardware acceleration techniques to improve encryption speed while maintaining strong resistance against cryptanalysis attacks. The Verilog-based implementation was synthesized and tested on an FPGA plat- form, demonstrating significant improvements in performance compared to conventional software-based encryption methods. Key performance metrics, including encryption/decryption speed, power consumption, and resource utilization, were analyzed to validate the effectiveness of the proposed design. Experimental results indicate that the optimized RC6 implementation achieves reduced execution time and lower power consumption, making it highly suitable for real-time security applications in embedded systems, IoT devices, and secure data transmission protocols. The study also compares the proposed architecture with existing FPGA-based cryptographic implementations to highlight its advantages in terms of scalability, flexibility, and resistance to attacks

Keywords:- Verilog, power efficiency, RC6 Algorithm, security.