Enhanced Test Pattern Generator using Modified LFSR

Built-In Self Test (BIST) is a widely adopted Design-for-Testability strategy that embeds test logic within integrated circuits for autonomous fault detection. Among various pattern generation techniques, Linear Feedback Shift Registers (LFSRs) are favored for their simplicity and low area overhead. However, conventional LFSRs generate pseudorandom patterns with high switching activity between successive test vectors, causing excessive dynamic power consumption during testing. This paper proposes an enhanced Test Pattern Generator (TPG) using a structurally modified LFSR incorporating a transition control mechanism to improve inter-vector correlation. The modification significantly reduces bit transitions between consecutive patterns, lowering switching activity and dynamic power. Results on ISCAS benchmark circuits demonstrate notable power reduction while maintaining comparable fault coverage, making the design suitable for low-power BIST applications in VLSI circuits.

Keywords: Test Pattern Generator, LFSR, BIST, Low Power Testing, Switching Activity, Fault Coverage, DFT, VLSI