Encryption and Decryption using optimized Reconfigurable Reversible Gate

Project Code :TVMA01

Objective

This paper explains an application of reconfigurable logic, Encryption of data, Decryption of the same data implemented using Verilog coding.

Abstract

In today’s technologies the power dissipation, delays, size, and heat are the toughest challenges to overcome in IC industries. If the computing element’s size is minimized, we can speed up the process and if the power loss is reduced, the heat dissipation will also be less. The preferable solution for these difficulties is the method of reversibility and QCA. The reversible computing is ever promising technology for the upcoming quantum computing technologies. The RLGs will decrease the power loss to a large extent, ideally to zero. If it is practically developed as an IC, then the complete world of electronic devices must be replaced, this initiates the new generation of the electronic world. This paper explains an application of reconfigurable logic, Encryption of data, Decryption of the same data implemented using Verilog coding. The design is verified through Xilinx Vivado software and the optimized delay is observed. The Encryption and Decryption process (E&D) is verified by the Simulation results.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

·         Xilinx Vivado2018.3/Xilinx ISE Tool.

·         HDL: Verilog.

Hardware Requirements:

·         Microsoft® Windows XP.

·         Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support.

·         512 MB RAM.

·         100 MB of available disk space.

Learning Outcomes

LEARNING OUTCOMES:

  • Basics of Digital Electronics.
  • Introduction to Verilog Coding.
  • Different modeling styles in Verilog.

o   Data Flow modeling.

o   Structural modeling.

o   Behavioral modeling.

o   Mixed level modeling.

·       About approximation computing.

  • Applications in real time.

·         Xilinx Vivado 2018.3/Xilinx ISE 14.7 Suite for design and simulation.

·         Generation of Netlist.

·         Solution providing for real time problems.

·         Project Development Skills:

o   Problem Analysis Skills.

o   Problem Solving Skills.

o   Logical Skills.

o   Designing Skills.

o   Testing Skills.

o   Debugging Skills.

o   Presentation Skills.

o   Thesis Writing Skills.

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