Efficient Architectures of FIR Filters using Distributed Arithmetic

Project Code :TVMAFE689

Objective

The objective of this project is to design and implement efficient architectures of FIR filters using distributed arithmetic for high-speed and low-power digital signal processing applications. It focuses on optimizing computation by replacing multipliers with look-up tables and adders to reduce hardware complexity. Different FIR filter architectures will be analyzed and compared based on performance metrics such as area, delay, and power consumption. Simulation and verification will be carried out to ensure functional accuracy and efficiency. The overall goal is to develop compact, high-performance FIR filter designs suitable for real-time signal processing systems.

Abstract

Abstract:

This research presents an overview of the Finite impulse response (FIR) filter architectures that utilize distributed arithmetic design (DAD). This paper reviews non-reconfigurable as well as reconfigurable FIR filter architectures using DA. General Multiply Accumulator (MAC) based FIR filter architectures require large chip area, consume more power and enforce a limitation on the order of filters. DAD technique is a bit serial operation which has high throughput processing capability, cost effective, area and power efficient. This paper presents different realizations of FIR filters using different DAD techniques namely LUT based DAD, LUT-Less DAD, shared LUT based DAD. This paper presents a comparative analysis of different DA based FIR filters and can form a basis for further work on DA based reconfigurable FIR filters

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