Designing of AES-128 Encryption Algorithm Using System Verilog VLSI
Objective
Hardware Realization of AES-128 • Implement the full AES-128 algorithm (10 rounds of SubBytes, ShiftRows, MixColumns, AddRoundKey) in SystemVerilog for synthesis. • Build a modular RTL design (e.g., separate modules for S-box, key expansion, round logic) to make it reusable and clear.
Abstract
Low-power digital systems are essential in modern embedded and Internet of Things (IoT) applications, where energy efficiency and reliable data communication are critical. Pulse counters are widely used to measure events such as sensor outputs, rotational speed, frequency, and energy consumption. This project presents the design and implementation of a low-power pulse counter integrated with a Serial Peripheral Interface (SPI) for efficient data transfer. The proposed system accurately counts input pulses while minimizing power consumption through optimized sequential logic and clock-gating techniques. The SPI interface enables reliable communication between the pulse counter and an external microcontroller or processor. The design achieves low power operation, scalability, and ease of integration, making it suitable for battery-powered and real-time embedded applications.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
8. Specifications:
Software Requirements:
· Xilinx ISE Tool/Xilinx Vivado
· HDL: System Verilog
Learning Outcomes
Learning Outcomes
· Understanding the AES-128 encryption algorithm and its core operations: SubBytes, ShiftRows, MixColumns, and AddRoundKey.
· Learning SystemVerilog HDL coding for designing combinational, sequential, and pipelined modules.
· Hands-on experience with FPGA implementation and simulation using Xilinx Vivado or VLS tools.
· Understanding low-power design techniques such as clock gating and resource optimization.
· Analyzing trade-offs between speed, area, and power in cryptographic hardware designs.
· Gaining knowledge of modular pipeline architectures for high-performance cryptography.
· Practical experience in testing, verification, and validation of secure hardware designs.
· Development of real-world skills in designing efficient encryption hardware suitable for embedded applications.
Related Projects
Paper Publishing
Request Call Back
Would you like to receive a free callback now?
Choose the best time for callback:
Leave your message and we will contact you as soon as possible
6-2-85/B, Old Maternity Hospital Road, Thyagaraja Nagar, Tirupati, Andhra Pradesh – 517501
+91 9030333433
+91 9393939065
0877-2261612
Disclaimer - Takeoff Edu Group Projects are not associated or affiliated with IEEE in any way. The IEEE Projects mentioned here are mentioned in the context of student projects, whose ideas are derived from IEEE publications, not projects of or by IEEE.
