Design of a Power-Aware Reconfigurable and Parameterizable Pseudorandom Pattern Generator for BIST-Based Applications
Objective
The objective of this project is to design and implement a power-aware, reconfigurable, and parameterizable pseudorandom pattern generator (PRPG) for BIST-based applications. It focuses on reducing power consumption while maintaining high fault coverage and flexibility in test pattern generation. The design will allow reconfiguration of parameters such as seed values and sequence length to support diverse testing requirements. Simulation and analysis will be carried out to evaluate performance metrics like power, area, and test efficiency. The overall goal is to develop an energy-efficient and adaptable PRPG architecture suitable for modern low-power VLSI testing environments
Abstract
Abstract
This paper presents a power-aware Reconfigurable Parameterizable Pseudorandom Pattern Generator (RP-PRPG) for a number of applications, including built in self-testing (BIST) and cryptography. Linear Feedback Shift Registers (LFSRs) are broadly utilized in pattern generation due to their efficiency and simplicity. However, the diversity of generated patterns, as well as their power consumption, improves through circuit modifications. This work explores enhancements to LFSR structures to achieve broader range of patterns with reduced power consumption for BIST-based applications. The proposed circuit constructed on the LFSR platform can be programmed to generate patterns with varying degrees of different LFSR configurations.NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
· Xilinx ISE Tool/Xilinx Vivado
· HDL: Verilog
Learning Outcomes
· Understand testing challenges in nanoscale multi-port memories
· Analyze coupling faults in bit lines and word lines
· Learn BIST-based memory test methodologies
· Design test strategies with minimal area overhead
· Evaluate trade-offs between test time and fault coverage
· Apply automated test generation tools in VLSI testing.
Related Projects
Paper Publishing
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