Design and Implementation of SRAM on FPGA and Verification Using UVM

Project Code :TVMAFE674

Objective

The objective of this project is to design and implement a Static Random Access Memory (SRAM) on an FPGA platform to achieve high-speed and efficient data storage. It focuses on developing a memory architecture with optimized area and power utilization. The design will be synthesized, implemented, and tested on FPGA hardware to verify its functionality and performance. Universal Verification Methodology (UVM) is used to create a reusable and robust verification environment. The goal is to ensure the correctness, reliability, and efficiency of the SRAM design through functional and timing verification

Abstract

Abstract:

This research focuses on the design, verification, and implementation of a 6T SRAM using HDL, UVM, and FPGA for performance optimization. A reusable UVM testbench ensures thorough verification of read and write operations, while coverage-driven verification verify all possible scenarios. System Verilog assertions enhance design correctness. The 6T SRAM model is simulated and synthesized using Vivado for functional verification. Additionally, a comparative analysis of 6T SRAM, Dual port 6T SRAM (DSRAM), and Pseudo static RAM (P6T SRAM) is conducted, focusing on power consumption, speed, and area utilization. The aims to develop an efficient memory architecture for high-speed, low-power applications, ensuring reliability and improved performance in digital systems.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.