Design and Implementation of Asynchronous Counter Using Reversible Logic Gates

Project Code :TVMAFE704

Objective

Reduce Power Dissipation • Use reversible logic because it ideally conserves information, leading to lower energy loss (heat) compared to irreversible circuits. • Specifically, target lower power consumption in the asynchronous counter by using reversible flip-flops.

Abstract

The present work, a low-power, high-performance asynchronous counter is designed, implemented and simulated using reversible logic. This reversible logic gates such as Feynman, Fredkin and Sayem gate are designed using transmission gates. The Sayem gate is designed using Feynman and Fredkin, whereas T-Flipflop is designed using Sayem and Feynman gate. A combination of all these reversible logic gates is used to design an asynchronous counter. As energy efficiency becomes a crucial concern in contemporary digital systems, especially in mobile and embedded applications. Reversible logic reduces power consumption by preserving information and preventing bit erasure, in contrast to conventional that experience power dissipation as a result of irreversible logic transitions. For reducing energy loss during processing, reversible logic presents a possible solution.

Keywords:- Verilog, power efficiency, reversible logic gates, asynchronous counters.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

·         Xilinx ISE14.7 Suite/Vivado2018.3 Tool.

·         HDL: Verilog.

Hardware Requirements:

·         Microsoft® Windows XP.

·         Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support.

·         512 MB RAM.

100 MB of available disk space.

Learning Outcomes

•      Basics of Digital Electronics

•      FPGA design Flow

•      Introduction to Verilog Coding

•      Different modeling styles in Verilog

o   Data Flow modeling

o   Structural modeling

o   Behavioral modeling

o   Mixed level modeling

•      Drawbacks of existing methods

•      Applications in real time

•      Xilinx ISE 14.7/Xilinx Vivado for design and simulation

•      Generation of Netlist

•      Solution providing for real time problems

•      Project Development Skills:

o   Problem Analysis Skills

o   Problem Solving Skills

o   Logical Skills

o   Designing Skills

o   Testing Skills.

o   Debugging Skills.

o   Presentation Skills.

o   Thesis Writing Skills

Demo Video

mail-banner
call-banner
contact-banner
Request Video