DESIGN AND IMPLEMENTATION OF 44 VEDIC MULTIPLIER WITH REDUCED TRANSISTOR COUNT AND COMPETITIVE POWER CONSUMPTION

The primary objective of “Design and Implementation of 44 Vedic Multiplier With Reduced Transistor Count and Competitive Power Consumption” is to design, implement, and evaluate an efficient 4×4 Vedic multiplier architecture that achieves significant reductions in transistor count, on-chip area, and propagation delay while maintaining competitive power consumption. Leveraging the ancient Vedic multiplication technique (specifically the Urdhva-Tiryagbhyam sutra), the work constructs basic logic blocks (AND, OR, half adders, full adders) and builds up a 4×4 multiplier in Cadence Virtuoso using 180 nm technology. The proposed design demonstrates approximately a 70 % improvement in area and about 73 % reduction in delay compared to a conventional CMOS Vedic multiplier, making it a promising candidate for low-area, high-performance digital arithmetic units.