Design and Evaluation of Low-Power Approximate Multipliers in Real-Time Image Applications

Approximate computing has emerged as an effective technique for reducing power consumption and improving performance in error-tolerant applications such as real-time image processing. Multipliers are among the most power-hungry arithmetic units, making them prime candidates for approximation. This work focuses on the design and evaluation of low-power approximate multipliers tailored for real-time image applications. Several approximate multiplier architectures are implemented and analyzed in terms of power, delay, area, and image quality metrics. Experimental results demonstrate significant power savings with minimal degradation in visual quality. The proposed designs offer an optimal trade-off between computational accuracy and hardware efficiency