Design and analysis of leading one or zero detector based approximate multipliers
Objective
Optimize power consumption, delay, and area using LOD/LZD-based approximation.
Abstract
Approximate multipliers are commonly used in error-tolerant applications to enhance circuit performance. Previous approximate Booth multipliers for signed multiplication tend to exhibit large relative errors when operands are near zero, while leading-one detector (LOD)-based multipliers are not energy-efficient due to the additional preprocessing module. In this paper, we propose a low-relative-error, leading-one/zero detector-based approximate multiplier (LOZDAM) for signed multiplication. This approach dynamically truncates operands based on the position of their most significant bits for signed complement data. The accuracy of the LOZDAM can be adjusted to meet the fault-tolerance requirements of different applications. Additionally, a compensation strategy is introduced to minimize the calculation error of LOZDAMs at a low cost.
Key Words——Approximate multiplier Low-power Leading one/zero detector Error compensation
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Block Diagram
Specifications
Software Requirements:
• Xilinx VIVADO Tool
• HDL: Verilog
Learning Outcomes
• Basics of Digital Electronics
• FPGA design Flow
• Introduction to Verilog Coding
• Different modeling styles in Verilog
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
• Drawbacks of existing methods
• Applications in real time
• Xilinx Vivado for design and simulation
• Generation of Netlist
• Solution providing for real time problems
• Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
Related Projects
Paper Publishing
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