1. To analyze the structural vulnerabilities in XOR-Arbiter Physical Unclonable Functions (PUFs), particularly how combining multiple arbiter chains affects security against modeling attacks. 2. To study the effectiveness of chosen-challenge attacks (CCA) on XOR-Arbiter PUF variants and understand how selective querying can leak information about the internal delay characteristics.
Physical Unclonable Functions (PUFs) are lightweight hardware security primitives used for device authentication, identification, and key generation. Among them, XOR Arbiter PUFs were introduced to enhance resistance against modeling attacks by combining multiple Arbiter PUF responses using XOR logic. However, despite this added complexity, XOR Arbiter PUFs remain vulnerable to advanced machine learning and chosen-challenge attacks. This work presents a detailed study on breaking XOR Arbiter PUFs using chosen challenge attacks, highlighting how an attacker can strategically select challenges to efficiently learn internal delay parameters. The study analyzes existing PUF architectures, their limitations, and proposes a secure countermeasure framework to improve robustness against such attacks.
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Software Requirements:
· Xilinx ISE14.7 Suite/Vivado2018.3 Tool.
· HDL: Verilog.
Hardware Requirements:
· Microsoft® Windows XP.
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support.
· 512 MB RAM.
· 100 MB of available disk space.
• Basics of Digital Electronics
• FPGA design Flow
• Introduction to Verilog Coding
• Different modeling styles in Verilog
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
• Drawbacks of existing methods
• Applications in real time
• Xilinx ISE 14.7/Xilinx Vivado for design and simulation
• Generation of Netlist
• Solution providing for real time problems
• Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills.
o Debugging Skills.
o Presentation Skills.
o Thesis Writing Skills