Area Efficient Approximate 4-2 Compressor and Probability-Based Error Adjustment for Approximate Multiplier
Objective
In this brief, we have presented a novel area efficient 4-2 compressor and a brand-new hybrid combination method of probabilistic adjustment employing approximate compressors for approximate multiplier.
Abstract
This work presents a novel 4-gate, 4-2 approximate compressor designed to enhance power savings in error-tolerant applications such as image processing, building upon existing designs from prior research. A hybrid multiplier is proposed, integrating these new compressors with a constant approximation technique and an error-correcting AND gate. Simulation results show that this hybrid multiplier achieves an effective balance of accuracy and performance, offering a 66% reduction in power-delay area product (PDAP) compared to a conventional precise multiplier.
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Block Diagram
Specifications
Software Requirements:
· Xilinx Vivado Tool
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to Verilog Coding
- Different modelling styles in Verilog
o Data Flow modelling
o Structural modelling
o Behavioural modelling
o Mixed level modelling
· Introduction to Probability-Based Error Adjustment for Approximate Multiplier
· Application to Real-Time Systems:
· Xilinx ISE 14.7/Xilinx Vivado for design and simulation
· Generation of Netlist
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
Thesis Writing SkillsDemo Video
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