An FPGA Implementation of a 16-bit Adder for Signed Magnitude Numbers

The implementation of arithmetic operations in Field-Programmable Gate Arrays (FPGAs) is crucial for digital systems requiring high-speed and parallel processing capabilities. This paper presents the design and implementation of a 16-bit adder for signed magnitude numbers using an FPGA. The proposed architecture employs a Carry Propagate Adder (CPA) as the core computational unit, combined with logic for handling signed magnitude representation. The design is implemented on a CORA Z7: ZYNQ-Z7000 FPGA board using Verilog HDL and synthesized in Vivado 2022.2. Simulation results confirm the correctness of the adder, with a fully combinational logic structure that eliminates latency. The architecture utilizes 57 LUTs, 18 slices, and 48 bounded IOBs, demonstrating an optimized balance between speed and resource efficiency. This work provides an efficient solution for real-time arithmetic computations involving signed numbers in FPGA-based applications. Future improvements may focus on power optimization, reducing hardware complexity, and extending support for additional arithmetic operations.