Project Code: TVMAFE793
Project Title:Design and Verification of Floating Point Multiplier for DSP ApplicationsView DetailsProject Code: TVMAFE779
Project Title:Energy Efficient High Performance 64bit ALU using Reversible Logic Based on Self Error Detection and Correction TechniqueView DetailsProject Code: TVMAFE777
Project Title:Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applicationsView DetailsProject Code: TVMAFE700
Project Title:Design of Asynchronous FIFO with Adjustable Input-Output Bit Width Based on VerilogView DetailsProject Code: TVMAFE721
Project Title:Breaking XOR Arbiter PUFs With Chosen Challenge AttackView DetailsProject Code: TVMAFE719
Project Title:Design of Power and Area Optimized 16 – bit MultiplierView DetailsProject Code: TVMAFE717
Project Title:Performance Analysis for Optimized ALU Design Using Carry Select Adder and Vedic MultiplierView DetailsProject Code: TVMAFE716
Project Title:Designing a High-Speed, Low-Area Three-Operand Binary Adder using Kogge-Stone, Han-Carlson, and Ladner-Fischer VLSI ArchitecturesView DetailsProject Code: TVMAFE714
Project Title:Performance Analysis of MAC Unit with Various Parallel AddersView DetailsProject Code: TVMAFE710
Project Title:An FPGA Implementation of a 16-bit Adder for Signed Magnitude NumbersView Details Items per page:
1 – 10 of 17
S.no | Project Code | Project Name | Action |
|---|---|---|---|
| 1 | TVMAFE793 | Design and Verification of Floating Point Multiplier for DSP Applicati... | |
| 2 | TVMAFE779 | Energy Efficient High Performance 64bit ALU using Reversible Logic Bas... | |
| 3 | TVMAFE777 | Design and evaluation of clock-gating-based approximate multiplier for... | |
| 4 | TVMAFE700 | Design of Asynchronous FIFO with Adjustable Input-Output Bit Width Bas... | |
| 5 | TVMAFE721 | Breaking XOR Arbiter PUFs With Chosen Challenge Attack | |
| 6 | TVMAFE719 | Design of Power and Area Optimized 16 – bit Multiplier | |
| 7 | TVMAFE717 | Performance Analysis for Optimized ALU Design Using Carry Select Adder... | |
| 8 | TVMAFE716 | Designing a High-Speed, Low-Area Three-Operand Binary Adder using Kogg... | |
| 9 | TVMAFE714 | Performance Analysis of MAC Unit with Various Parallel Adders | |
| 10 | TVMAFE710 | An FPGA Implementation of a 16-bit Adder for Signed Magnitude Numbers |
Items per page:
1 – 10 of 17
Project Code: TVMAFE793
Project Title:Design and Verification of Floating Point Multiplier for DSP ApplicationsView DetailsProject Code: TVMAFE779
Project Title:Energy Efficient High Performance 64bit ALU using Reversible Logic Based on Self Error Detection and Correction TechniqueView DetailsProject Code: TVMAFE777
Project Title:Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applicationsView DetailsProject Code: TVMAFE700
Project Title:Design of Asynchronous FIFO with Adjustable Input-Output Bit Width Based on VerilogView DetailsProject Code: TVMAFE721
Project Title:Breaking XOR Arbiter PUFs With Chosen Challenge AttackView DetailsProject Code: TVMAFE719
Project Title:Design of Power and Area Optimized 16 – bit MultiplierView DetailsProject Code: TVMAFE717
Project Title:Performance Analysis for Optimized ALU Design Using Carry Select Adder and Vedic MultiplierView DetailsProject Code: TVMAFE716
Project Title:Designing a High-Speed, Low-Area Three-Operand Binary Adder using Kogge-Stone, Han-Carlson, and Ladner-Fischer VLSI ArchitecturesView DetailsProject Code: TVMAFE714
Project Title:Performance Analysis of MAC Unit with Various Parallel AddersView DetailsProject Code: TVMAFE710
Project Title:An FPGA Implementation of a 16-bit Adder for Signed Magnitude NumbersView Details Items per page:
1 – 10 of 17
S.no | Project Code | Project Name | Action |
|---|---|---|---|
| 1 | TVMAFE793 | Design and Verification of Floating Point Multiplier for DSP Applicati... | |
| 2 | TVMAFE779 | Energy Efficient High Performance 64bit ALU using Reversible Logic Bas... | |
| 3 | TVMAFE777 | Design and evaluation of clock-gating-based approximate multiplier for... | |
| 4 | TVMAFE700 | Design of Asynchronous FIFO with Adjustable Input-Output Bit Width Bas... | |
| 5 | TVMAFE721 | Breaking XOR Arbiter PUFs With Chosen Challenge Attack | |
| 6 | TVMAFE719 | Design of Power and Area Optimized 16 – bit Multiplier | |
| 7 | TVMAFE717 | Performance Analysis for Optimized ALU Design Using Carry Select Adder... | |
| 8 | TVMAFE716 | Designing a High-Speed, Low-Area Three-Operand Binary Adder using Kogg... | |
| 9 | TVMAFE714 | Performance Analysis of MAC Unit with Various Parallel Adders | |
| 10 | TVMAFE710 | An FPGA Implementation of a 16-bit Adder for Signed Magnitude Numbers |
Items per page:
1 – 10 of 17
Project Code: TVMAFE793
Project Title:Design and Verification of Floating Point Multiplier for DSP ApplicationsView DetailsProject Code: TVMAFE779
Project Title:Energy Efficient High Performance 64bit ALU using Reversible Logic Based on Self Error Detection and Correction TechniqueView DetailsProject Code: TVMAFE777
Project Title:Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applicationsView DetailsProject Code: TVMAFE700
Project Title:Design of Asynchronous FIFO with Adjustable Input-Output Bit Width Based on VerilogView DetailsProject Code: TVMAFE721
Project Title:Breaking XOR Arbiter PUFs With Chosen Challenge AttackView DetailsProject Code: TVMAFE719
Project Title:Design of Power and Area Optimized 16 – bit MultiplierView DetailsProject Code: TVMAFE717
Project Title:Performance Analysis for Optimized ALU Design Using Carry Select Adder and Vedic MultiplierView DetailsProject Code: TVMAFE716
Project Title:Designing a High-Speed, Low-Area Three-Operand Binary Adder using Kogge-Stone, Han-Carlson, and Ladner-Fischer VLSI ArchitecturesView DetailsProject Code: TVMAFE714
Project Title:Performance Analysis of MAC Unit with Various Parallel AddersView DetailsProject Code: TVMAFE710
Project Title:An FPGA Implementation of a 16-bit Adder for Signed Magnitude NumbersView Details Items per page:
1 – 10 of 17
S.no | Project Code | Project Name | Action |
|---|---|---|---|
| 1 | TVMAFE793 | Design and Verification of Floating Point Multiplier for DSP Applicati... | |
| 2 | TVMAFE779 | Energy Efficient High Performance 64bit ALU using Reversible Logic Bas... | |
| 3 | TVMAFE777 | Design and evaluation of clock-gating-based approximate multiplier for... | |
| 4 | TVMAFE700 | Design of Asynchronous FIFO with Adjustable Input-Output Bit Width Bas... | |
| 5 | TVMAFE721 | Breaking XOR Arbiter PUFs With Chosen Challenge Attack | |
| 6 | TVMAFE719 | Design of Power and Area Optimized 16 – bit Multiplier | |
| 7 | TVMAFE717 | Performance Analysis for Optimized ALU Design Using Carry Select Adder... | |
| 8 | TVMAFE716 | Designing a High-Speed, Low-Area Three-Operand Binary Adder using Kogg... | |
| 9 | TVMAFE714 | Performance Analysis of MAC Unit with Various Parallel Adders | |
| 10 | TVMAFE710 | An FPGA Implementation of a 16-bit Adder for Signed Magnitude Numbers |
Items per page:
1 – 10 of 17
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