▷ VLSI Projects Using Verilog for M.Tech

S.no	Project Code	Project Name
1	TVPGTO589	A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... DSP Core\|Xilinx Vivado\|Xilinx ISE
2	TVPGTO590	A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... DSP Core\|Cadence EDA\|Xilinx ISE
3	TVPGTO591	A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... DSP Core\|Cadence EDA\|Xilinx Vivado
4	TVPGTO592	Constant-time Synchronous Binary Counter with Minimal Clock Period Design for Testability\|Xilinx ISE
5	TVPGTO593	Constant-time Synchronous Binary Counter with Minimal Clock Period Design for Testability\|Xilinx Vivado
6	TVPGTO594	Design and Analysis of Approximate Compressors for Balanced Error Accu... Arithmetic Core\|Xilinx ISE
7	TVPGTO595	Design and Analysis of Approximate Compressors for Balanced Error Accu... Arithmetic Core\|Xilinx Vivado
8	TVPGTO596	Design and Verification of 16 bit RISC Processor Using Vedic Mathemati... DSP Core\|Xilinx ISE
9	TVPGTO597	Design and Verification of 16 bit RISC Processor Using Vedic Mathemati... DSP Core\|Xilinx Vivado
10	TVPGTO598	Design of Ultra-Low Power Consumption Approximate 4-2 Compressors Base... Arithmetic Core\|Xilinx ISE

Items per page:

1 – 10 of 144

Project Code: TVPGTO589

Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications

DSP Core| Xilinx Vivado| Xilinx ISE

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Project Code: TVPGTO590

Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications

DSP Core| Cadence EDA| Xilinx ISE

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Project Code: TVPGTO591

Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications

DSP Core| Cadence EDA| Xilinx Vivado

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Project Code: TVPGTO592

Project Title:Constant-time Synchronous Binary Counter with Minimal Clock Period

Design for Testability| Xilinx ISE

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Project Code: TVPGTO593

Project Title:Constant-time Synchronous Binary Counter with Minimal Clock Period

Design for Testability| Xilinx Vivado

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Project Code: TVPGTO594

Project Title:Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC Operator

Arithmetic Core| Xilinx ISE

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Project Code: TVPGTO595

Project Title:Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC Operator

Arithmetic Core| Xilinx Vivado

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Project Code: TVPGTO596

Project Title:Design and Verification of 16 bit RISC Processor Using Vedic Mathematics

DSP Core| Xilinx ISE

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Project Code: TVPGTO597

Project Title:Design and Verification of 16 bit RISC Processor Using Vedic Mathematics

DSP Core| Xilinx Vivado

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Project Code: TVPGTO598

Project Title:Design of Ultra-Low Power Consumption Approximate 4-2 Compressors Based on the Compensation Characteristic

Arithmetic Core| Xilinx ISE

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Items per page:

1 – 10 of 144

S.no	Project Code	Project Name
1	TVPGTO589	A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... DSP Core\|Xilinx Vivado\|Xilinx ISE
2	TVPGTO590	A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... DSP Core\|Cadence EDA\|Xilinx ISE
3	TVPGTO591	A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... DSP Core\|Cadence EDA\|Xilinx Vivado
4	TVPGTO592	Constant-time Synchronous Binary Counter with Minimal Clock Period Design for Testability\|Xilinx ISE
5	TVPGTO593	Constant-time Synchronous Binary Counter with Minimal Clock Period Design for Testability\|Xilinx Vivado
6	TVPGTO594	Design and Analysis of Approximate Compressors for Balanced Error Accu... Arithmetic Core\|Xilinx ISE
7	TVPGTO595	Design and Analysis of Approximate Compressors for Balanced Error Accu... Arithmetic Core\|Xilinx Vivado
8	TVPGTO596	Design and Verification of 16 bit RISC Processor Using Vedic Mathemati... DSP Core\|Xilinx ISE
9	TVPGTO597	Design and Verification of 16 bit RISC Processor Using Vedic Mathemati... DSP Core\|Xilinx Vivado
10	TVPGTO598	Design of Ultra-Low Power Consumption Approximate 4-2 Compressors Base... Arithmetic Core\|Xilinx ISE

Items per page:

1 – 10 of 144

Project Code: TVPGTO589

Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications

DSP Core| Xilinx Vivado| Xilinx ISE

View Details

Project Code: TVPGTO590

Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications

DSP Core| Cadence EDA| Xilinx ISE

View Details

Project Code: TVPGTO591

Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications

DSP Core| Cadence EDA| Xilinx Vivado

View Details

Project Code: TVPGTO592

Project Title:Constant-time Synchronous Binary Counter with Minimal Clock Period

Design for Testability| Xilinx ISE

View Details

Project Code: TVPGTO593

Project Title:Constant-time Synchronous Binary Counter with Minimal Clock Period

Design for Testability| Xilinx Vivado

View Details

Project Code: TVPGTO594

Project Title:Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC Operator

Arithmetic Core| Xilinx ISE

View Details

Project Code: TVPGTO595

Project Title:Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC Operator

Arithmetic Core| Xilinx Vivado

View Details

Project Code: TVPGTO596

Project Title:Design and Verification of 16 bit RISC Processor Using Vedic Mathematics

DSP Core| Xilinx ISE

View Details

Project Code: TVPGTO597

Project Title:Design and Verification of 16 bit RISC Processor Using Vedic Mathematics

DSP Core| Xilinx Vivado

View Details

Project Code: TVPGTO598

Project Title:Design of Ultra-Low Power Consumption Approximate 4-2 Compressors Based on the Compensation Characteristic

Arithmetic Core| Xilinx ISE

View Details

Items per page:

1 – 10 of 144

S.no	Project Code	Project Name
1	TVPGTO589	A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... DSP Core\|Xilinx Vivado\|Xilinx ISE
2	TVPGTO590	A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... DSP Core\|Cadence EDA\|Xilinx ISE
3	TVPGTO591	A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... DSP Core\|Cadence EDA\|Xilinx Vivado
4	TVPGTO592	Constant-time Synchronous Binary Counter with Minimal Clock Period Design for Testability\|Xilinx ISE
5	TVPGTO593	Constant-time Synchronous Binary Counter with Minimal Clock Period Design for Testability\|Xilinx Vivado
6	TVPGTO594	Design and Analysis of Approximate Compressors for Balanced Error Accu... Arithmetic Core\|Xilinx ISE
7	TVPGTO595	Design and Analysis of Approximate Compressors for Balanced Error Accu... Arithmetic Core\|Xilinx Vivado
8	TVPGTO596	Design and Verification of 16 bit RISC Processor Using Vedic Mathemati... DSP Core\|Xilinx ISE
9	TVPGTO597	Design and Verification of 16 bit RISC Processor Using Vedic Mathemati... DSP Core\|Xilinx Vivado
10	TVPGTO598	Design of Ultra-Low Power Consumption Approximate 4-2 Compressors Base... Arithmetic Core\|Xilinx ISE

Items per page:

1 – 10 of 144

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Communications and Crypto Core
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