Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators

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Project Code: TVMATO815

Project Title:Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators

Communications| Xilinx Vivado| Cadence EDA

Project Code: TVMATO818

Project Title:Novel Architecture for Lifting Discrete Wavelet Packet Transform With Arbitrary Tree Structure

DSP Core| Xilinx Vivado

Project Code: TVMATO822

Project Title:Fault Detection Mechanism using Improved Watchdog Timer for Safety Application

Communications| Xilinx Vivado

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S.no	Project Code	Project Name	Action
1	TVMATO815	Toward Functional Safety of Systolic Array-Based Deep Learning Hardwar... Communications\|Xilinx Vivado\|Cadence EDA
2	TVMATO818	Novel Architecture for Lifting Discrete Wavelet Packet Transform With ... DSP Core\|Xilinx Vivado
3	TVMATO822	Fault Detection Mechanism using Improved Watchdog Timer for Safety App... Communications\|Xilinx Vivado

Items per page:

1 – 3 of 3

Related Topics

Front End Domains

Arithmetic Core
Communications
DSP Core
FPGA

Back End Domains

Core Memories
Low Power VLSI
Transistor Logic
Nano Technology

Tools

Xilinx ISE
FPGA
Cadence EDA
Xilinx Vivado

Others

Matlab Interfacing

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