VLSI IMPLEMENTATION OF VEDIC MULTIPLIER

Vedic arithmetic is an old Indian science, discovered from ancient Indian sculptures (Vedas). High-speed more multiple is the primary block in processor architecture. Vedic mathematics developed from a special method of calculations of 16-sutras. This chapter presents VLSI architecture implementation of a 16-bit multiplier with compressors, which shows significant improvement over conventional add shift multiplier. Vedic mathematics developed from 16 principles known as sutras. The technique of Vedic more multiple is Urdhva-Triyakbhyam (Vertically and Crosswise) sutra. This sutra was customarily used in the ancient history of Indian culture to multiply two decimal numbers with minimum time. The hardware architecture of Vedic multiplier is similar to array multiplier. In the performance of digital signal processors which frequently perform multiplication, much depends on the calculation speed of the multiplier block. The existing method of multiplication shift-add, booth multiplication requires hardware resources, which leads to high power consumption. The present method of Vedic multiplication based on the compressor block is focused on the reduction of interconnect wire. The multiplier is implemented using Verilog HDL with Xilinx Vivado2018.3 and the constrain areas, power and delay optimize using underlying block.