Also Available Domains Xilinx Vivado|Xilinx ISE
This paper proposes the VLSI implementation of Fully parallel and CSD FIR filter architecture. In this technique, the area and power optimization are achieved by the incorporation of Vedic multiplier and Koggestone adder instead of traditional multiplier and adder.
This paper proposes the VLSI implementation of fully parallel and CSD FIR filter architecture. In this technique, the area and power optimization are achieved by the incorporation of Vedic multiplier and Koggstone adder instead of traditional multiplier and adder. Furthermore, a valid comparison of aforesaid architecture for 8-tap and 16-tap FIR filters is made in both linear and tree topology. Further, the proposed filter architecture is also analyzed in the presence of a pipeline mechanism.
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Software Requirements:
· Tool: Xilinx ISE 14.7 /Xilinx Vivado2018.3
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP,
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills