VLSI Implementation of Error Detection and Correction Codes for Space Engineering

Abstract

This paper presents a VLSI implementation of a novel error detection and correction scheme tailored for space engineering, targeting on-chip memory reliability in the presence of environmental factors such as cosmic radiation and extreme temperatures. The proposed 2-dimensional code utilizes a divide-symbol approach, employing XOR operations to analyze diagonal, parity, and check bits during encoding. A sophisticated decoding process involves syndrome calculation and region selection, efficiently identifying and correcting errors. Simulations using Xilinx Vivado demonstrate the scheme's effectiveness, yielding low power consumption and minimal area utilization compared to existing methods. This innovative error correction methodology offers a promising solution for enhancing memory reliability in space applications, addressing issues caused by multiple cell upsets induced by radiation.