Abstract

For multiplier dominated applications such as digital signal processing, wireless communications, and computer applications, high speed multiplier designs has always been a
primary requisite. In this paper a high performance 64x64 bit redundant binary (RB) multiplier have been designed by using recently proposed redundant binary encoding approach to
eliminate the error correcting word and a delay efficient parallel prefix Ling adder for final redundant binary to normal binary (RB-NB) conversion. Since redundant binary (RB)
representation allows carry-free addition and adaptability, it has been used in 64x64 bit high-performance RB multiplier design for summation of partial product terms. The design of multiplier also reduces redundant partial product accumulation stage when eliminating the error correcting word which improves the complexity and the critical path delay. The performance of RB multiplier design compared with conventional RB modified booth encoding multiplier (CRBMBE). The comparison is based on synthesis result obtained by synthesizing both multiplier architectures targeting a Xilinx ISE/vivado FPGA in terms of area and delay analysis.