VLSI design of 128-point finite field FFT multiplier

Finite field arithmetic plays a crucial role in modern digital signal processing, error control coding, and cryptographic systems. Fast Fourier Transform (FFT) over finite fields, also known as Number Theoretic Transform (NTT), is widely used to accelerate polynomial multiplication and convolution operations. This project presents the VLSI design of a 128-point finite field FFT multiplier optimized for high speed and low power consumption. The proposed architecture exploits parallelism inherent in FFT algorithms while employing efficient modular multiplication and addition units suitable for finite field operations. By carefully designing butterfly units, modular arithmetic blocks, and pipeline stages, the multiplier achieves reduced computational latency and improved throughput. The design is well suited for ASIC and FPGA implementations in high-performance and security-critical applications.