Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Schedule and Sub Bytes Block Optimization

Information security has a major role in the development next generation communication system, where more randomization in the secret key is required for improved security without adding any complexity over existing cryptography algorithms. In the recent years Symmetric key algorithms like Advanced Encryption Standard (AES) is widely used in many network security applications. In Symmetric key algorithms hierarchical physical and key based transformation blocks are used for both encryption and decryption process. Hardware optimization also plays a vital role for reducing the computational complexity and power consumption rate of AES core. In this paper 256-bit AES algorithm is proposed with optimized Key schedule and Sub bytes blocks for Area and Power optimization. Here the hardware optimization is accomplished by reusing the S-box block and share the common resource for all internal operations for only 32-bit operations rather than 128-bit operations. The proposed model allows to re-use the same hardware in a pipelined fashion. Recently, many key management schemes have been proposed, each with its own particular strengths, weaknesses, and applications under certain circumstances. In addition to this paper also proposes an extension of a dynamic key extraction in cryptosystem which can maximize the randomness by adding outer layer security. Finally, the performance metrics like randomness, design complexity, reliability, and discriminative properties are compared with existing works. Through Experimental results the metrics of proposed key generation like randomness, distinctiveness.