Very Fast, High-Performance 5-2 and 7-2 Compressors in CMOS Process for Rapid Parallel Accumulations
Also Available Domains Cadence EDA|Tanner EDA
Objective
This paper presents the new design methodology for speed performance enhancement of 7 ? 2 & 5-2 compressor structures. The compressor circuits are used in multipliers. Through this architecture, the delay will be less.
Abstract
In this project, a design methodology for ultra-high-speed 5-2 and 7-2 compressors has been illustrated to avoid the Carry Rippling Problem in the existing compressors. The power consumption of the proposed compressors is also reduced since the basic circuits such as XOR and multiplexer are designed using Transmission gate logic. Simulation results show that the proposed multiplier has High performance in terms of delay when compared with the previous designs.
Keywords: 5-2 compressor, 7-2 compressor, High performance, Transmission gate logic.
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Block Diagram
Specifications
Software Requirements:
- Tanner EDA
- Technology files:180nm
Hardware Requirements:
- Microsoft® Windows XP
- Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
- 512 MB RAM
- 100 MB of available disk space
Paper Publishing
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