Also Available Domains Transistor Logic|Cadence EDA
This paper presents the new design methodology for speed performance enhancement of 7 ? 2 & 5-2 compressor structures. The compressor circuits are used in multipliers. Through this architecture, the delay will be less.
In this project, a design methodology for ultra-high-speed 5-2 and 7-2 compressors has been illustrated to avoid the Carry Rippling Problem in the existing compressors. The power consumption of the proposed compressors is also reduced since the basic circuits such as XOR and multiplexer are designed using Transmission gate logic. Simulation results show that the proposed multiplier has High performance in terms of delay when compared with the previous designs. All the designs are implemented using 180nm technology in Tanner EDA tool.
Keywords: 5-2 compressor, 7-2 compressor, High performance, Transmission gate logic.
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