The project is to design and implement an automated bus ticketing system using Verilog for hardware description. The system will handle ticket issuance, fare calculation, and user interaction through a digital interface.
This paper is a synthesis of practical investigation and theoretical analysis. Using Verilog HDL language to research a automatic bus ticketing system. The design of this bus ticketing system takes convenience, quickness and simplicity as the core, and takes saving time for passengers as the guide design. It completes the main process of buying bus tickets for passengers. Firstly, this paper studies the development of bus ticketing system and then studies the basic components of bus ticketing system. Through Xilinx VIVADO development software to do schematic input mode, this paper designs the bus automatic ticket selling system which composed of selector module, coin calculation module and collectionmodule . The paper also simulates the selector module, coin calculation module and collection module on Xilinx VIVADO.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Software Requirements:
Β· Xilinx VIVADO.
Hardware Requirements:
Β· Digilent Basys-3 if Required.
Β· Verilog HDL concepts.
1. Behavioural modelling.
2. Always block.
3. Case statements.
4. Casex statements.
5. Data-flow modelling.
6. Assign statements.
7. FSM concepts.
8. Simple digital electronics concepts.