Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes
Also Available Domains Communications and Crypto Core|Xilinx Vivado
Objective
Finally, this paper discusses the generalization of the proposed scheme to codes with larger error correction capabilities.
Abstract
In this project, a novel Scan-Based Logic Built-In Self-Test (LBIST) is proposed and it can be used to control the scan-shift power to an arbitrary level. High power consumption in LBIST, is a crucial issue that can cause over-testing, reliability degradation, chip damage.
The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. The effectiveness of the proposed method is designed using Xilinx ISE 14.7
Keywords: Built-In-Self-Test (BIST), Linear Feedback Shift Register (LFSR), Test Pattern Generator, Scan design
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Specifications
Learning Outcomes
v Front End : Xilinx 14.3 for Synthesis, Simulation and Implementation
v This software’s where Verilog source code can be used for design implementation.
Paper Publishing
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