Also Available Domains Xilinx Vivado|Xilinx ISE
The main aim of this paper is to generate the true random numbers through 3 edge ring oscillators to increase the hardware security as well as increase the randomness of the output.
Our design uses a new technique with a time-to-digital converter to effectively acquire jitter accumulated independently by each edge. As a part of the security evaluation, we present the stochastic model of the TRNG’s digital noise source and estimate a lower bound of the min-entropy per random bit. Starting from the obtained entropy bound, we propose a procedure for selecting and implementing an area-efficient and throughput-optimal post processing function based on the best-known linear codes that will increase the output min-entropy rate. The proposed TRNG exquisitely balances low design effort and resource consumption with high throughput and a high min entropy rate, making it more suitable for randomness-demanding and resource-constrained platforms than the state-of-the-art.
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Specifications:
Software Requirements:
· Xilinx ISE/Xilinx Vivado Tool
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP,
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes:
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
· Xilinx ISE 14.7/Xilinx Vivado for design and simulation
· Generation of Netlist
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
Thesis Writing Skills