Toward Designing High-Speed Cost-Efficient Quantum Reversible Carry Select Adders

Compared to classical computing implementations, reversible arithmetic adders provide a promising platform for quantum computation models in digital systems. They are particularly useful in specific applications such as cryptography and natural language processing. One of the key advantages of reversible logic is its ability to minimize energy wastage by preventing thermal dissipation effectively.This study presents a detailed exploration of reversible arithmetic adders, focusing on the development of new carry-select adders (CSLA) designed using quantum and reversible logic principles. A total of five reversible CSLA designs are proposed and systematically analyzed. These designs are evaluated based on multiple criteria, including speed, quantum cost, and area efficiency, and are compared to previously published schemes.The evaluation framework is designed for n-bit size blocks, ensuring scalability and flexibility. Each design is described in a generic manner, making it capable of implementing carry-select adders of any size. Among these proposed designs, the study identifies and presents an optimized reversible adder circuit. This circuit addresses the challenge of quantum propagation delay and achieves a well-balanced trade-off between quantum cost and performance.Notably, the proposed reversible adder reduces calculation delay significantly. For 16-bit, 32-bit, 64-bit, and 128-bit adders, the delays are reduced by 66%, 73%, 82%, and 87%, respectively. Furthermore, these improvements are achieved while maintaining a consistently lower quantum cost across all cases, demonstrating the efficiency and practicality of the proposed designs.

Keywords: —Carry select adder, reversible logic, quantum computing, quantum cost, quantum delay.