The hybrid full adder following circuit XOR gate and 2:1 multiplexer using pass transistor along with PFAL adiabatic logic style and 32-bit adders

This paper presents a comprehensive design and analysis of a hybrid full adder circuit that integrates XOR gates and 2:1 multiplexers utilizing pass transistor logic, combined with PFAL (Pulsed-Fully Adiabatic Logic) adiabatic logic style. The primary objective is to enhance the performance and power efficiency of arithmetic operations in digital circuits.

The proposed hybrid full adder leverages the strengths of XOR gates and multiplexers to achieve high-speed and low-power operation. The use of pass transistor logic in the design improves circuit efficiency by reducing power consumption compared to traditional static CMOS logic. The PFAL adiabatic logic style further contributes to power savings by minimizing energy dissipation during the switching process, thus making it well-suited for energy-constrained applications.

Simulation results demonstrate significant improvements in power efficiency and speed, validating the effectiveness of the proposed design. This approach offers a promising solution for high-performance and low-power digital arithmetic units, contributing to the advancement of energy-efficient computing technologies. Therefore these paper we are going to implement carry look ahead adder & carry save adder for 32 bits using with PFAL logic full adder circuit on the tanner eda tool.