Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs

Project Code :TVMABE319

Objective

The objective is to design and implement ternary logic circuits at the transistor level using a combination of depletion-mode and conventional enhancement-mode MOSFETs. This project aims to explore multi-valued logic (MVL) as an alternative to binary logic, focusing on reducing circuit complexity, interconnect overhead, and power consumption. By bridging ternary logic with binary-compatible interfaces, the study evaluates the feasibility, performance, and efficiency of implementing compact, low-power logic circuits suitable for future digital and nanoelectronics systems.

Abstract

The application of artificial intelligence (AI) requires advanced computation to address complex problems. However, the improvement of binary computing systems supporting these applications is approaching their limits due to atomic-level scaling. Regarding this challenging situation, ternary computing is gaining more attention due to its better data saving/computing/moving capability. Thus, ternary logic based on various devices was proposed, but these circuits are still encountering issues of high-power consumption, low operating speed, and challenges in manufacturing compared to silicon-based circuits. Therefore, this paper presents a methodology for designing ternary logic based on Depletion-mode metaloxide-semiconductor field-effect transistor (DEPFET) and multi-threshold voltage complementary metal– oxide–semiconductor (MTCMOS). Our silicon-based devices are easier to manufacture and support highspeed/low-power operations through our complementary ternary logic. Our balanced ternary full adder (BTFA) is 9.70× better energy efficiency than the latestcarbon nanotube field-effect transistor (CNTFET) based BTFA. We also propose the first methodology to design a ternary cell layout in multi-height standard cell design. We propose an algorithm for the best ternary cell layout and a concept of integrated layout that reduces area when required cells are close to each other

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

· Tool: H-Spice

Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Learning Outcomes

Learning Outcomes:

Introduction to Digital electronics
Introduction to logic gates
Importance of Transistors

Types of adders
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
Comprehend DEPFET (depletion-mode MOSFET) and multi-threshold CMOS integration for ternary logic
- How DEPFET devices (which turn ON even at zero gate bias) can help realize the “middle” logic state (0.5 VDD) in a ternary inverter or logic gate.
- How combining DEPFET with multi-threshold (LVT/HVT) CMOS devices enables a complementary ternary logic scheme with lower static power and faster switching.