Speed Enhancement in the Performance of Two Phase Clocked Adiabatic Static CMOS Logic Circuits & Implementation of 4 bit bidirectional shift register using 2PASCL Adiabatic logic

The primary objective of this work is to enhance the operating speed and energy efficiency of digital circuits by employing Two-Phase Clocked Adiabatic Static CMOS Logic (2PASCL). Conventional CMOS logic suffers from significant dynamic power dissipation due to charging and discharging of load capacitances, especially at high clock frequencies. Adiabatic logic, by contrast, enables energy recovery from the load capacitance, thereby reducing power consumption.