In this paper, we propose a scalable approximate multiplier design, scaleTRIM, that approximates the multiplication operation using fitted linear functions, also referred to as linearization. We show that multiplication operations can be completely replaced by low-cost addition and bit-wise shift operations by exploiting linearization. Moreover, our proposed design utilizes a lookup table (LUT) based compensation unit as a novel error-reduction method. In essence, input operands are truncated to a reduced bit-width representation (i.e., h bits) based on their leading-one positions. Then, a curve fitting method is employed to map the product term to a linear function. Additionally, a piecewise constant error-correction term is used to reduce the approximation error. To compute the piecewise constant, we divide the function space into M segments and average the errors within each segment.
we propose a scalable approximate multiplier design, scaleTRIM, that approximates the multiplication operation using fitted linear functions, also referred to as linearization. We show that multiplication operations can be completely replaced by low-cost addition and bit-wise shift operations by exploiting linearization. Moreover, our proposed design utilizes a lookup table (LUT)-based compensation unit as a novel error-reduction method. In essence, input operands are truncated to a reduced bit-width representation (i.e., h bits) based on their leading-one positions. Then, a curve-fitting method is employed to map the product term to a linear function. Additionally, a piecewise constant error-correction term is used to reduce the approximation error. To compute the piecewise constant, we divide the function space into M segments and average the errors within each segment. In particular, our multiplier supports various degrees of truncation and error compensation to offer a range of accuracy-efficiency trade-offs. The proposed multiplier improves the Mean Relative Error Distance (MRED) by about 15.2% while satisfying the efficiency constraint and improves the Power Delay Product (PDP) by about 22.8% while satisfying the accuracy and efficiency constraints compared to different state-of-the-art approximate multipliers. From a usability perspective, our evaluation of the proposed design for image classification using Deep Neural Networks (DNNs) demonstrates that scaleTRIM offers a better accuracy-efficiency trade-off than state-of the-art approximate multiplier designs.
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Software Requirements
FPGA Design Tools
· Xilinx Vivado Design Suite (2023.2 or later)
· Vivado Synthesis
· Vivado Implementation
· Vivado Simulator
Hardware Description Language
· Verilog HDL
· Design and implement a scalable truncation-based approximate multiplier using Verilog HDL.
· Understand the principles of approximate computing and hardware optimization.
· Implement leading-one detection, operand truncation, and linearization techniques.
· Design LUT-based error compensation mechanisms for reducing approximation errors.
· Perform FPGA synthesis and analyze area, power, delay, and Power-Delay Product (PDP).
· Compare the proposed architecture with conventional approximate multipliers using hardware performance metrics.
· Gain practical experience in FPGA-based low-power VLSI design for edge AI and DNN accelerator applications.
· Develop skills in configurable arithmetic circuit design suitable for energy-efficient embedded systems.
