Reversible Logic Based 1-bit Comparator using QCA
Also Available Domains Arithmetic Core
Objective
The main objective of this paper is to implement the reversible logic in QCA technology in order to achieve low power consumption with fast performance.
Abstract
Heat and energy dissipation are the immense problems in today’s processor design. These problems can be overcome if the reversible logic is used for the design implementation. In this paper, the 1-bit comparator based on reversible logic is proposed. Further, the reversible logic gates used in the proposed design are implemented using “Quantum-dot Cellular Automata (QCA) nanotechnology”. QCA is viable technology among various nanotechnology through which reversible logic can be implemented at device level with low energy, less area and high speed. The simulation is backed by the QCA Designer tool. The proposed design is single layered which is also optimized for area, energy and delay.
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Block Diagram
Specifications
Software Requirements:
· QCA Designer tool
· HDL: Verilog.
Hardware Requirements:
o Microsoft® Windows XP.
o Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support.
o 512 MB RAM.
o 100 MB of available disk space.
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to Quantum dot cellular automata (QCA)
- Introduction to Combinational circuits.
- Knowledge on SRAM.
- Knowledge on LUT.
- Concept on CLB.
- QCA Designer tool for design and simulation.
- Applications in real time.
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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