Revamping Verilog Semantics for Foundational Verification

Project Code :TVMAFE732

Objective

The objective of this project is to revamp the semantics of Verilog to address challenges in modern verification processes. By refining the language's syntax and semantics, the project aims to improve its expressiveness and precision for complex digital system design. The goal is to enhance the verification capabilities, making it easier to validate the correctness of hardware descriptions. The project also seeks to introduce new methodologies for error detection, reducing verification time and effort. Ultimately, this will improve the reliability and efficiency of hardware designs using Verilog in foundational verification tasks.

Abstract

In formal hardware verification, particularly for Register-Transfer Level (RTL) designs in Verilog, model checking has been the predominant technique. However, it suffers from state explosion, limited expressive power, and a large trusted computing base (TCB). Deductive verification offers greater expressive power and enables foundational verification with a minimal TCB. Nevertheless, Verilog's standard semantics, characterized by its nondeterministic and global scheduling, pose significant challenges to its application. To address these challenges, we propose a new Verilog semantics designed to facilitate deductive verification. Our semantics is based on least fixpoints to enable cycle-level functional evaluation and modular reasoning. For foundational verification, we prove our semantics equivalent to the standard scheduling semantics for synthesizable designs. We demonstrate the benefits of our semantics with a modular verification of a pipelined RISC-V processor's functional correctness and progress guarantees. All our results are mechanized in Rocq

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