Renovated 32 Bit ALU Using Hybrid Techniques
Also Available Domains Xilinx Vivado
Objective
The main aim of this project is to design an Efficient Vedic mathematics and refurbished approximate adder to form a 32 bit Efficient ALU and the major target of this works is to get Efficient ALU by reducing the area, power, and delay.
Abstract
In this project, we are proposing an efficient ALU design by using Efficient Vedic mathematics and efficient adder. In the present scenario there is an increasing demand for enhancing the ability of processors, which is a challenging one. The most preferred module of a CPU is ALU which performs the arithmetic and logical operations along with some digital transactions. This multi-purposed ALU circuit can conditionally perform various functions depending on control inputs. It presents a technique called “Vedic Mathematics” for designing the multiplier that is fast as compared to other multipliers based on mathematical techniques that have been in practice for a long time. A processor’s speed depends prominently on its multiplier as multipliers are used in various fields where processing of some signal is essential. The multiplier is implemented with an efficient CSA adder is proposed. For addition approximated CLA has been implemented. By this the performance of the proposed ALU is optimized in terms of area, delay and power. The effectiveness of the proposed method is synthesized and simulated using XilinxISE14.7/Xilinx Vivado.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Software Requirements:
· Xilinx ISE Tool/Xilinx Vivado
· HDL: Verilog
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
- Basics of Digital Electronics
- VLSI design Flow
- Introduction to Verilog Coding
- Different modeling styles in Verilog
o Data Flow modeling
o Structural modeling
o Behavioral modeling
o Mixed level modeling
- Introduction to Arithmetic circuits
- Knowledge on ALU
- Different control units and instructions
- Applications in real time
· Xilinx ISE 14.7/Xilinx Vivado for design and simulation
· Generation of Netlist
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
Paper Publishing
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