Reconfigurable Radix-2k×3 Feed Forward FFT Architectures

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVREFE19_53

Objective

A proposed feedforward radix-3 FFT is applied in the architecture, empowering the FFT processor to achieve high parallelisms.

Abstract

Due to the increasing demand for high throughput and low-cost mobile devices, design of high-parallel reconfigurable FFT processors has become more and more important. However, FFT lengths varied, designing a multi length FFT processor with the requirement meet has becomeunprecedentedly challenging, especially as the FFT lengths includes non-power-of-two. In this paper, reconfigurable mixed radix 2k×3-point feedforward FFT architectures are proposed.It can be realized as any power-of-two parallelism to achieve the sweet spot, with performs high enough to meet the requirement and still promise a reasonable cost. A proposed feedforwardradix-3 FFT is applied in the architecture, empowering the FFT processor to achieve high parallelisms. An 8-parallel 128- 2048/1536-point FFT processor for the 4G LTE system is implemented with TSMC 90nm technology. Compared to the existing designs, this work offers a high-throughput and high area-efficiency solution for mixed-radix FFT operation.

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Block Diagram

Learning Outcomes

Basics of Digital Communications, Verilog.

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