RASC: A Low-Power Reconfigurable 4-2 Adder-Subtractor-Compressor
Objective
1. To study the design principles of arithmetic circuits, particularly adders, subtractors, and compressors, and understand their role in high-speed digital systems. 2. To design a 4-2 adder-subtractor-compressor module that is reconfigurable, allowing the circuit to perform addition, subtraction, or compression operations based on control signals.
Abstract
In modern digital signal processing and arithmetic circuits, efficient utilization of hardware resources with reduced power consumption and high performance remains critical. This paper presents RASC, a low‑power and reconfigurable 4‑2 adder‑subtractor‑compressor architecture. RASC supports multiple arithmetic operations — addition, subtraction, and compression — within a single adaptive hardware block. The design leverages optimized logic restructuring and reconfigurable datapaths to minimize switching activities and power usage without penalizing performance. Simulation and synthesis results demonstrate significant improvement in power efficiency and area utilization compared to traditional designs, making RASC suitable for low‑power embedded systems and high‑throughput applications.
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Block Diagram
Specifications
Software Requirements
- Xilinx Vivado Design Suite (2020.2 or later)
- Verilog HDL for RTL design and implementation
- Vivado Simulator (XSIM) for functional and timing verification
- MATLAB (optional) for GPR data preprocessing, noise modeling, and result validation
Hardware Requirements
- Microsoft® Windows 10 / Windows 11 (64-bit)
- Intel® Core™ i5 / i7 Processor or equivalent
- Minimum 8 GB RAM
- Minimum 500 MB free disk space
Learning Outcomes
By studying the RASC architecture and related arithmetic designs, learners will be able to:
Understand the trade‑offs between fixed and reconfigurable arithmetic units.
Analyze the impact of carry propagation and logic depth on latency.
Design low‑power arithmetic circuits using logic sharing and optimization techniques.
Integrate reconfigurable arithmetic blocks into larger digital systems.
Evaluate performance metrics such as area, power, and throughput in hardware design.
Paper Publishing
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