Protecting Analog Circuits Using Switch Mode Time Domain Locking

Project Code :TVMABE321

Objective

Lock analog circuit behavior by integrating a time-domain switching mechanism controlled by a key. Use random-key–based switching phases instead of conventional fixed-clock signals, ensuring that only with the correct key and correct phase alignment does the analog circuit operate as intended.

Abstract

Analog circuits remain susceptible to a wide range of supply chain threats, including piracy, overproduction, counterfeiting, and reverse engineering. In this work, we propose a Switch Mode Time Domain Locking (SMDL) scheme to enhance the security of analog circuits. The proposed approach embeds a locking mechanism into the circuit’s time-domain operation by utilizing random key–dependent switching phases in place of conventional fixed clocks. The switching phases are determined by a secret key of arbitrary length, and only a correct key (CK) with proper phase alignment enables circuit functionality.

The SMDL technique is applicable to various switch-mode analog circuits, such as filters, amplifiers, and regulators. To demonstrate its effectiveness, we implement the scheme on a folded cascode amplifier (FCA) and a switched-capacitor bandgap reference (BGR) circuit. In the FCA implementation, a low-power biasing technique is incorporated to minimize power consumption while maintaining gain and stability. The implementation, carried out in 45-nm CMOS technology, shows that the use of an incorrect key (IK) introduces nearly 100% variation in circuit behavior, thereby ensuring a high level of security.

Index Terms— Analog hardware security, time-domain locking, low-power analog design, circuit obfuscation, bandgap reference (BGR).

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

· Tool: Cadence virtuoso

Hardware Requirements:

· Microsoft® Windows XP

· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

· 512 MB RAM

· 100 MB of available disk space

Learning Outcomes

Introduction to Digital electronics
Introduction to logic gates
Importance of Transistors

Types of adders
NMOS/PMOS/CMOS Technologies
How to design circuits using Transistor logic?
CLA with adibiatic logic
Applications in Real time.
Importance of logic gates in memory.

Cadence for design and simulation

· Understanding of Threats:
Develop knowledge of supply chain vulnerabilities specific to analog circuits.

· Mastery of SMDL Concept:
Gain expertise in how switch mode time-domain locking secures analog designs using random key–driven switching phases.

· Integration of Low-Power Techniques:
Learn how methods such as current-reuse biasing, SAPON, and LECTOR can reduce power consumption in secured analog blocks.

· Hands-On Implementation:
Acquire skills in applying SMDL to practical analog designs like folded cascode amplifiers (FCA) and switched-capacitor bandgap reference (BGR) circuits.

· Research and Innovation Capability:
Build the ability to propose and validate new hardware security techniques that balance security, power, and performance for advanced analog/mixed-signal systems.