Power Efficient Multiplier Design for Error Resilient Edge Applications

Project Code :TVMAFE828

Objective

Edge devices require low-power and efficient hardware to support data-intensive computations in real-time applications. Traditional multipliers are computationally demanding and consume considerable power; however, approximate circuits are used in applications requiring low-power consumption and high-performance. The approximate multiplier is the key arithmetic function in many error-tolerant applications, such as signal processing, image processing, etc. This letter presents a power-efficient approximate multiplier design tailored for error-resilient applications on edge devices. The proposed design employs an approximate 4:2 compressor based on input reordering. Input reordering is used to reduce the number of combinations which leads to low power consumption. The experimental analysis demonstrates the efficacy of the proposed approximate multiplier that achieves power and area savings.

Abstract

Modern edge computing applications, including image processing, signal processing, machine learning, and IoT devices, demand arithmetic hardware that delivers high computational performance while maintaining low power consumption. Conventional multipliers provide high computational accuracy but consume significant power, area, and delay, making them less suitable for battery-powered edge devices. This project presents a power-efficient approximate multiplier architecture based on an input-reordered approximate 4:2 compressor. The proposed compressor minimizes switching activity by reducing redundant input combinations through intelligent input reordering, thereby lowering dynamic power consumption while maintaining acceptable computational accuracy. The approximate compressor is integrated into a tree-based multiplier architecture to achieve high-speed multiplication with reduced hardware complexity. The proposed design is implemented using Verilog HDL and validated through simulation and FPGA synthesis in Xilinx Vivado. Experimental results demonstrate considerable reductions in power consumption, logic utilization, and propagation delay while preserving sufficient computational accuracy for error-resilient applications such as deep neural networks, multimedia processing, and edge AI inference. The proposed multiplier offers an efficient solution for resource-constrained edge devices requiring low-power and high-performance arithmetic hardware.

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Block Diagram

Specifications

Hardware Requirements

FPGA Board: Xilinx Artix-7 / Basys 3 FPGA

Software Requirements

FPGA Design Tools

Xilinx Vivado Design Suite (2023.2 or later)
Vivado Synthesis
Vivado Implementation
Vivado Simulator

Hardware Description Language

Verilog HDL

Learning Outcomes

Design an approximate multiplier using an input-reordered 4:2 compressor in Verilog HDL.
Analyze approximate arithmetic circuits for low-power VLSI applications.
Implement and verify the multiplier using Xilinx Vivado.
Evaluate FPGA resource utilization, timing performance, power consumption, and delay.
Compare exact and approximate multipliers using performance metrics such as area, power, delay, and power-delay product.
Develop expertise in low-power arithmetic circuit design for edge computing and AI hardware accelerators.